1. Field of the Invention
The present invention relates to metal interconnection formation in semiconductor devices, and more particularly, to a method for forming a metal interconnection of a semiconductor device, in which, in a single damascene process using lower and upper inter-metal dielectric (IMD) films, a nitridation layer is thinly deposited and annealed before forming a trench in the upper IMD film. This obtains a constant trench depth by avoiding over-etching or under-etching when forming the trench, thereby preventing the occurrence of openings and voids in a copper interconnection.
2. Discussion of the Related Art
An electrical interconnection in a semiconductor device is formed by patterning a metal layer, which is typically made of copper to improve the operating speed of the device. To overcome etching difficulties, the metal interconnection is typically formed by a damascene process, which may be a dual damascene process or a single damascene process.
In a dual damascene process, an etch-stop layer and an IMD film are stacked and are then etched to form a via hole or a contact hole and a trench in the stacked layers. A diffusion prevention layer and a seed layer are sequentially formed on the entire surface of resulting structure, namely, on the substrate including the via hole and the trench. Here, the seed layer of a copper interconnection is a Cu seed layer, so that the diffusion prevention layer is a copper barrier metal film. The copper is deposited by electroplating and is then planarized by, for example, by chemical-mechanical polishing, to form simultaneously a via plug in the via hole and the copper interconnection in the trench.
During copper deposition, however, a lower transistor may be contaminated by diffusion of copper atoms through the contact hole. Therefore, the electrical contact in such cases is formed by a single damascene process in which a deposition of tungsten is used to first fill the via hole. Then, the copper interconnection is formed only in the trench above the contact hole. A related art method for forming a metal interconnection of a semiconductor device using a single damascene process is illustrated in FIGS. 1A and 1B.
Referring to FIGS. 1A and 1B, a contact hole is formed in a first IMD film 101 formed on a semiconductor substrate (not shown), and a tungsten plug 102 fills the contact hole. A second IMD film 103 is deposited on the first IMD film 101 to cover the filled contact hole and is then selectively etched to form a trench in which a copper barrier metal film 104 and a copper 105 are sequentially deposited.
When etching to form the trench, however, under-etching (FIG. 1A) or over-etching (FIG. 1B) may be experienced. For example, in the under-etching shown in FIG. 1A, there is an opening in the copper interconnection. In the over-etching shown in FIG. 11B, an excessive deposition of the copper barrier metal film 104 tends to occur along the upper edges of the tungsten plug 102 and thus creates an overhang 106 under which a void 107 may be generated. The openings in the copper interconnection and the voids in the copper deposition increase the resistance of the metal interconnection, thereby degrading device characteristics.